1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and more particularly to a current sense amplifier which amplifies a difference current signal between current signals on complementary data lines in a static random access memory (SRAM) to detect a logical value stored in a memory cell.
2. Description of the Related Art
Recently, in the field of semiconductor memories, demands for high integration of memory cells and for reduction of an operation voltage are increasing. However, the reduction of the operation voltage results in reduction of an operation speed for reading data stored in a memory cell and further, a noise margin to correctly decide the data is also reduced. Therefore, it is important to use a sense amplifier which detects the logical value as a difference between current values on the data lines or voltage values on the data lines.
FIG. 1 shows a block diagram of a static random access memory (SRAM). SRAM 100 mainly has a decoder and a control circuit 102, a word line driver 103, a pre-charge circuit 104, a memory cell array 105, a column switch 106, a sense amplifier 107, a write amplifier 108 and an input/output circuit 109. An area surrounded by a broken line 130 corresponds to a part for one column.
First, a read operation to read data from a memory cell in the SRAM 100 will be explained. In order to read a logical value from the memory cell in the memory cell array 105, first, an address, a clock signal and a control signal 101 is supplied to the decoder and the control circuit 102. The decoder and the control circuit 102 supplies an output signal to the word line driver 103 and also supplies a column selection signal 111 to the column switch 106. Next, a pre-charge signal 121 is supplied to the pre-charge circuit 104 by the decoder and the control circuit 102, then a bit line 113 and an inverted bit line 114 are pre-charged. Then, a word selection signal is supplied to the memory cell array 105 through a word selection line 110, then the memory cell in the memory cell array 105 is activated. The logical value stored in the memory cell is supplied to the bit line 113 and the inverted bit line 114. Next, a sense amplifier enable signal 112 is supplied to the sense amplifier 107 from the decoder and the control circuit 102 so that the sense amplifier 107 is activated. The logical values output on the bit line 113 and the inverted bit line 114 are fed to the sense amplifier 107 through the column switch 106 and are amplified by the sense amplifier 107. The logical value amplified by the sense amplifier 107 is output from the SRAM 100 through the input/output circuit 109 as the output data.
Next, a write operation to write data to the memory cell in the SRAM 100 will be explained. First, input data 120 is supplied to the input/output circuit 109 and is amplified by the write amplifier 108. The input data 120 amplified by the write amplifier 108 is supplied to the memory cell array 105 through the column switch 106. Simultaneously, the address, the clock signal and the control signal 101 is supplied to the decoder and the control circuit 102 as described in the read operation and the input data 120 is written to the memory cell selected by the address.
FIG. 2 shows an example of the sense amplifier 107 for one data bit constructed by a conventional sense amplifier. The sense amplifier 200 as shown in FIG. 2 is of a current detection type for a high speed operation. For example, this kind of sense amplifier is described in Japanese patent number 2551346. The sense amplifier 200 has P-channel metal oxide field effect transistors (as referred to PMOS, hereinafter) 201 and 202 and N-channel metal oxide field effect transistors (as referred to NMOS, hereinafter) 203, 204 and 205. A drain of the PMOS 201 is connected to a drain of the NMOS 203. A drain of the PMOS 202 is connected to a drain of the NMOS 204. A source of the NMOS 203, a source of the NMOS 204 and a drain of the NMOS 205 are connected each other. A source of the NMOS 205 is connected to a ground and the sense amplifier enable signal 112 is supplied to a gate of the NMOS 205. A gate of the PMOS 201, a gate of the NMOS 203 and the drain of the PMOS 202 are connected each other. A gate of the PMOS 202, a gate of the NMOS 204 and the drain of the PMOS 201 are also connected each other. A source of the PMOS 201 and a source of the PMOS 202 are two input terminals of the sense amplifier 200. The source of the PMOS 201 is connected to the data bus 115 in FIG. 1 and the source of the PMOS 202 is connected to the inverted data bus 116 in FIG. 1. An output terminal 117 and an inverted output terminal 118 are two output terminals of the sense amplifier 200.
The sense amplifier 200 quickly amplifies a current difference value supplied to the source of the PMOS 201 and the source of the PMOS 202 by means of a positive feedback, then outputs the logical value stored in the memory cell through the column switch 106 as shown in FIG. 1.
FIG. 3 shows another example of the sense amplifier 107 for one data bit constructed by another conventional sense amplifier. The sense amplifier 300 as shown in FIG. 3 is of a current detection type for a stable operation against noise. For example, this kind of sense amplifier is described in Laid-open Japanese patent application number 2-230694. 
The sense amplifier 300 has a PMOS 301 and a PMOS 302, and an NMOS 301, an NMOS 304 and an NMOS 305. A drain of the PMOS 301 is connected to a drain of the NMOS 303. A drain of the PMOS 302 is connected to a drain of the NMOS 304. A source of the NMOS 303, a source of the NMOS 304 and a drain of the NMOS 305 are connected each other. A source of the NMOS 305 is connected to a ground and the sense amplifier enable signal 112 is supplied to a gate of the NMOS 305. A gate of the PMOS 301, a gate of the NMOS 304 and the drain of the NMOS 304 are connected each other. A gate of the PMOS 302, a gate of the NMOS 303 and the drain of the NMOS 303 are also connected each other. A source of the PMOS 301 and a source of the PMOS 302 are two input terminals of the sense amplifier 300. The source of the PMOS 301 is connected to the data bus 115 in FIG. 1 and the source of the PMOS 302 is connected to the inverted data bus 116 in FIG. 1. An output terminal 117 and an inverted output terminal 118 are two output terminals of the sense amplifier 300.
The sense amplifier 300 quickly amplifies a current difference value supplied to the source of the PMOS 301 and the source of the PMOS 302 by means of a positive feedback circuit constructed by the PMOS 301 and the PMOS 302, and outputs the logical value stored in the memory cell through the column switch 106 as shown in FIG. 1. In this sense amplifier 300, a negative feed circuit constructed by the NMOS 303 and the NMOS 304 prevents inappropriate operation caused by noise applied from outside the SRAM 100.
However, the sense amplifier 200 described above quickly amplifies the noise applied to the data bus 115 and the inverted data bus 116 while the logical value from the memory cell is being amplified because of its high speed operation. If the noise has an opposite polarity from the logical value to be amplified, then the output of the sense amplifier may be inverted against the correct logical value stored in the memory cell.
On the other hand, the sense amplifier 300 as shown in FIG. 3 is robust against the noise, however, the speed of the operation to detects the logical value stored in the memory cell is low.
It is a general object of the present invention to provide a semiconductor memory device, in which the above disadvantages are eliminated.
A more specific object of the present invention is to provide a semiconductor memory device, which has a sense amplifier that is stable against noise, has a large output amplitude, can operate with high speed and has low power.
The above objects of the present invention are achieved by a semiconductor memory device which comprises a memory cell array having a plurality of memory cells, complementary data bus lines connected to said memory cells in said memory cell array and a sense amplifier. The sense amplifier is connected to the memory cells through the complementary data bus lines and amplifies a difference between current values on said complementary data bus lines associated with a logical value stored in the memory cell. The sense amplifier has a positive feedback circuit having a plurality of differential pairs constructed by transistors.
According to the invention, it is possible to construct a sense amplifier which has a plurality of source inputs, so that sources of the transistors of one differential pair can be connected to the complementary data bus lines and sources of the transistors of other differential pairs can be connected to a voltage source. Therefore, the output level of the sense amplifier can reach the source voltage level by means of the transistors connected to the voltage source. As a result, the semiconductor memory device having the high speed sense amplifier with a large noise margin can be achieved.